This invention relates to crosspoint switching arrays. More particularly, it is concerned with crosspoint switching arrays employing a matrix of crosspoint switches for connecting any one of a plurality of inputs to any one of a plurality of outputs.
A conventional switching array for connecting any one of a plurality of M inputs to any one of a plurality of N outputs employing a matrix of crosspoint switches S is illustrated by FIG. 1. The array is shown arranged in a matrix of M rows by N columns with a switch S at each crosspoint for connecting one of the M rows with one of the N columns. Any M input port can be connected to any N output port by closing the appropriate one of the switches S.
In such an array the switching speed between an input port and an output port is slowed by the stray capacitances of the rows, columns, and switches. It is apparent that the switching speed is decreased as the size of the array or number of switching nodes is increased, increasing the length of the row and column connecting lines.